A Secure Dynamically Programmable Gate Array Based on Ferroelectric Memory

The field programmable gate array (FPGA) market is expanding because FPGAs enable faster development times and lower development costs than mask programmable gate arrays (MPGAs).1) However, the conventional SRAM-based FPGA requires offchip, non-volatile PROMs to store configuration data, which increases the total device cost and the board area. To provide a low-cost solution for field programmable devices, we have developed a non-volatile, 8-context, dynamically programmable gate array (DPGAnote)) using ferroelectric RAM (FeRAM) technology. The developed configuration memory, which consists of a SRAM-based 6-transistor/4-ferroelectric-capacitor cell, has an access time comparable to that of a standard SRAM. It also has a non-destructive read operation and a stable data recall scheme. In addition, the contents of the configuration memory are securely protected. We have fabricated a prototype DPGA that combines 0.35 μm CMOS and FeRAM technologies. Using this device, we have executed the Data Encryption Standard (DES) functions at up to 51 MHz at 3.3 V. We confirmed that the minimum non-volatile operating voltage is 1.5 V.